Digital Verification Engineer — SystemVerilog / UVM

Category	Semiconductor / IC
Location	Japan（On-site）
Employment	To be agreed
Salary	Negotiable
Posted	Oct 23, 2026

Overview

Urgent chip-verification opening for module and full-chip validation.

Japan; specific worksite, salary, employment terms, start date and relocation/visa support must be confirmed for the assignment.

Responsibilities

• Build and run module/full-chip verification with SystemVerilog and UVM.
• Manage simulation, regression and coverage closure, including fault-injection verification.

Requirements

• SystemVerilog and UVM verification skills are required.
• Preferred: automotive chip verification experience.
• Bachelor’s degree in semiconductors, electronics or a related field.
• Working proficiency in English OR Japanese; both are not required by this brief.
• Relevant hands-on experience and willingness to work on-site in Japan long term.

Skills

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